hardware - Why the INOUT doesn't work? -

i making circuit handles read , write operations registers , uses single bus transfer data between registers, problem when reading bus (a register reading bus) works well, when trying assign value in register not working. note if used signal write work !!!

my code:

library ieee; use     ieee.std_logic_1164.all;  -- entity: circuit -- description: organizes read , write operation bus -- n size of word in register, default 16 -- m number of selection lines in decoder, 2 ^ m -- number of registers in cicuit  -- data_bus: bus used transfer data -- reg_read: input decoder determines register read bus. -- reg_write: input decoder determines register write bus. -- read: read signal -- write: write signal -- clk: clock -- rst: reset  entity circuit   generic( n : integer := 16;             m : integer := 2);   port(data_bus : inout std_logic_vector(n-1 downto 0);        reg_read, reg_write : in std_logic_vector(m-1 downto 0);        read, write, clk, rst : in std_logic);  end circuit;   architecture circuit_arch of circuit  -- tristate buffers component tsb   generic ( n : integer := 16);    port ( e   : in  std_logic;           input  : in  std_logic_vector (n-1 downto 0);          output : out std_logic_vector (n-1 downto 0)); end component;   -- registers component ndff   generic ( n : integer := 16);   port( clk,rst,e : in std_logic;         d : in std_logic_vector(n-1 downto 0);         output : out std_logic_vector(n-1 downto 0));  end component;  -- decoders component ndecoder   generic ( n : integer := 4);   port(e : in std_logic;        s : in std_logic_vector( n-1 downto 0);        output : out std_logic_vector(2 ** n - 1 downto 0));  end component;  type output array (0 (2 ** m) - 1) of std_logic_vector (n-1 downto 0); signal read_dec, write_dec : std_logic_vector(2 ** m - 1 downto 0); signal regs_out : output; signal test : std_logic_vector(n-1 downto 0); begin     -- generate decoders   dec1: ndecoder generic map(m) port map(read, reg_read, read_dec);   dec2: ndecoder generic map(m) port map(write, reg_write, write_dec);      -- generate registers   loop1: in 0 (2 ** m) - 1 generate      lbl1: ndff generic map(n) port map(clk, rst,read_dec(i),data_bus, regs_out(i));    end generate;    -- generate tristate buffers   loop2: j in 0 (2 ** m) - 1 generate      lbl2: tsb generic map(n) port map(write_dec(j), regs_out(j), data_bus);    end generate;  end circuit_arch; 

if @ lbl1 in generate statement you'll find portmap:

 lbl1: ndff generic map(n) port map(clk, rst,read_dec(i),data_bus, regs_out(i)); 

is positionally associative. while port declaration reflected in component declaration shows order:

port( clk,rst,e : in std_logic;         d : in std_logic_vector(n-1 downto 0);         output : out std_logic_vector(n-1 downto 0)); 

showing read_dec(i) register load enable.

and read buffers:

  -- generate tristate buffers   loop2: j in 0 integer(2 ** m) - 1 generate      lbl2: tsb generic map(n) port map(write_dec(j), regs_out(j), data_bus);    end generate; 

show write_dec(j).

and examining decodes generating them shows:

  -- generate decoders   dec1: ndecoder generic map(m) port map(read, reg_read, read_dec);   dec2: ndecoder generic map(m) port map(write, reg_write, write_dec);  

read corresponds read_dec , write corresponds write_dec.

it looks have enables reversed registers loads , register output buffer enables.

there more, without mvce answering can't beyond basic eyeballing , analyzing.

and reason paebbels asked target implementation practical purposes tristate internal buffers restricted asic implementations.