verilog - Which region are continuous assignments and primitive instantiations with #0 scheduled -

all #0 related code examples have found related procedural code (ie code inside begin-end). continuous assignments , primitive instantiations? ieee 1364 & ieee 1800 (verilog & systemverilog respectively) give 1 line description can find (quoting version of ieee 1364 under section name "the stratified event queue"):

an explicit 0 delay (#0) requires process suspended , added inactive event current time process resumed in next simulation cycle in current time.

i read documents , talked few engineers have been working verilog long before ieee std 1364-1995. in summary, inactive region failed solution synchronizing flip-flops verilog's indeterminate processing order. later verilog created non-blocking assignments (<=) , resolved synchronizing indeterminate order. inactive region left in scheduler not break legacy code , few obscure corner cases. modern guidelines avoid using #0 because creates race conditions , may hinder simulation performance. performance impact don't care small designs. run huge designs mixed rtl transistor level modules. small performance gains add , not having debug rouge race conditions time savers.

i've ran test case removing/adding #0 verilog primitives on large scale designs. simulators have notable changes others not. difficult tell doing better job following lrm or has smarter optimizer.

adding per-compile script remove hard coded forms of #0, easy enough. challenge parameterized delay. need create generate blocks avoid inactive region? feels introduce more problems solve:

generate   if ( rise > 0 || fall > 0)     tranif1 #(rise,fall) ipassgate ( d, s, g );   else     tranif1              ipassgate ( d, s, g );   if ( rise > 0 || fall > 0 || decay > 0)     cmos #(rise,fall,decay) i1 ( out, in, ng, pg );   else     cmos                    i1 ( out, in, ng, pg );   if (delay > 0)     assign #(delay) io = drive ? data : 'z;   else     assign          io = drive ? data : 'z; endgenerate 

verilog primitives , continuous assignments have been verilog since beginning. believe parameterized delay has been around longer inactive region. haven't found documentation on recommendation or explanation these conditions. local network of verilog/systemverilog gurus unsure region should run in. there detail overlooking or gray area in language? if gray area, how determine way implanted?

an accepted answer should include citation version of ieee1364 or ieee1800. or @ least way proof of concept testing.

this easy one. section 28.16 gate , net delays of 1800-2012 lrm section 7.14 gate , net delays of 1364-2005 lrm both say

for both gates , nets, default delay shall 0 when no delay specification given. means

gatename instancename (pins); 

is equivalent writing

gatename #0 instancename (pins); 

i'm not sure text quoted came from, section 4.4.2.3 inactive events region of 1800-2012 lrm says

if events being executed in active region set, explicit #0 delay control requires process suspended , event scheduled inactive region of current time slot process can resumed in next inactive active iteration.

the key text delay control, procedural construct. #0 inactive event applies procedural statements.

the problem procedural #0's move race conditions, don't eliminate them. have add multiple serial #0's move away races condition, don't know how many because piece of code adding #0's. @ uvm code; it's littered messy #0's because did not take time code things properly.