verilog - Up Down counter code -

i need in project counter counts or down 0 20. did counter code , it's working in active hdl. need show numbers in 7-segment in nexys 3 fpga board.

i have code of segment, have problem when call module of segment - giving me error in active hdl. can please tell me error?

this current code :

module main     #(parameter n=7)     (     input switch,     input button,     input fastclk,     output [3:0] enable,     output reg[6:0] out     );         wire[n:0]count;     wire slowclk;      clock c1(fastclk,slowclk);     updown u1(switch,button,slowclk,count);     segment s1([3:0]count,[7:4]count,fastclk,enable,out);      endmodule   module clock(fastclk,slowclk); //clock code     input fastclk;     output wire slowclk;     reg[25:0]period_count = 0;      @(posedge fastclk)         begin             period_count <= period_count + 1;         end     assign slowclk = period_count[25]; endmodule  module updown // updown counter #(parameter n=7)         (     input switch,     input button,     input clk,     output reg [n:0]count=8'd0,     );     @(posedge clk)     begin          if(switch == 1 && button == 1)  // countup 0 20             begin                  if(count == 8'd20)                     count <= 0 ;                  else                      count <= count +1;              end         else if(switch == 0 && button == 1) // countdown 20 0         begin                  if(count == 8'd0)                     count <= 8'd20 ;                  else                      count <= count -1;              end          else count <=8'd0;       end endmodule  module mux(a,b,sel,y); // 2x1 multiplexer     input [3:0]a;     input [3:0]b;     input sel;     output [3:0]y;     reg [3:0]y;      @(*)         begin              if(sel==0)                 y=a;             else                  y=b;              end endmodule  module hex7seg(input wire [3:0]x , output reg[6:0]a_to_g); // hex 7seg code      @(*)          case(x)             0: a_to_g = 7'b0000001;              1: a_to_g = 7'b1001111;             2: a_to_g = 7'b0010010;             3: a_to_g = 7'b0000110;             4: a_to_g = 7'b1001100;             5: a_to_g = 7'b0100100;             6: a_to_g = 7'b0100000;             7: a_to_g = 7'b0001111;             8: a_to_g = 7'b0000000;             9: a_to_g = 7'b0000100;             'ha: a_to_g = 7'b0001000;             'hb: a_to_g = 7'b1100000;             'hc: a_to_g = 7'b0110001;             'hd: a_to_g = 7'b1000010;             'he: a_to_g = 7'b0110000;             'hf: a_to_g = 7'b0111000;             default: a_to_g = 7'b0000001;         endcase endmodule  module segment (a,b,fast,enable,seg7);     input [3:0]a;     input [3:0]b;     input fast;     output [3:0] enable;     output [6:0] seg7;     wire [3:0]e1 = 4'b1110;     wire [3:0]e2 = 4'b1101;     wire slow;     wire [3:0]number;      clock c1(fast,slow);     mux m1(a,b,slow,number);     mux m2(e1,e2,slow,enable);     hex7seg h1(number,seg7);  endmodule 

you have small error in segment module initialization part of code:

segment s1([3:0]count,[7:4]count,fastclk,enable,out);  

this part of code should little bit different:

segment s1(count[3:0],count[7:4],fastclk,enable,out);